Most conventional techniques for digital to analog conversion require both high performance of analog circuitry, such as opertional amplifiers, and digital circuitry for counting, sequencing, and data storage. This has tended to result in hydrid circuits consisting of one or more bi-polar analog integrated circuit chips and an MOS chip to perform the digital functions. High performance and fairly complex signal processing has recently become possible on a single monolithic chip due to the face that very accurate capacitor ratios could be obtained in MOS technology to replace cumbersome conventional techniques such as diffused resistors, complex thin film process or ion implanted resistors. Using switched capacitor circuits reduces cost and power consumption significantly. The major problem with existing switched capacitor digital to analog converters is that all these circuits are sensitive to parasitic capacitances associated with the main capacitors of the circuit and are therefore incapable of delivering high resolution of ten bit accuracy and maintaining their monotonic characteristic. Another problem with existing circuits is that the area of silicon occupied by capacitors increases exponentially as a function of the number of input bits. To date, it has so far been impossible to get enough accuracy for ten bit resolution with reasonable silicon area. Lastly, the third major problem associated with existing digital to analog converters (DACs) is that the limiting factor on the conversion rate is always dictated by the current to voltage converting amplifier.
The circuit disclosed herein combines several new techniques to overcome the above mentioned problems. This new digital to analog converter is designed such that it is completely insensitive to parasitic capacitors associated with both plates of each capacitor which exists in the circuit so that very high resolution could be obtained. Secondly, a new variable gain technique, which could be defined as analog shift and add circuit, has been utilized to reduce the total capacitance needed for a ten bit DAC from 1025 unit capacitors to 63 unit capacitors. Finally, the circuit has been designed in such a way that a voltage mode output is available from the chip at the same speed that conversion actually happens. Therefore, there is no need for off chip amplification which limits speed.
In accordance with the present invention, the circuitry of the switched capacitor digital to analog converter utilizes five binary weighted input capacitors and a digital circuit to perform multiplexing and generating the necessary timing. A combination of input capacitors and feedback capacitors gives rise to an output voltage in an amount proportional to digital input bits in a binary fashion such that in the first step, the output voltage is proportional to the first five least significant bits divided by 32 and the second step the output voltage would be equal to the previous value plus a voltage proportional to the five most significant bits again divided by 32. Therefore, at the end of the second step, the output voltage is an analog voltage proportional to the binary input bits times the reference voltage divided by 1024.